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GYLQ-161L-10-L，100Gbps 10km LR4 Duplex LC QSFP28
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- Product Description
- Specification Parameters
- Product Dimensions
- Installation Instructions
- Equipment Grounding
- Power Connection
- Ordering Information
-
- Commodity name: GYLQ-161L-10-L，100Gbps 10km LR4 Duplex LC QSFP28
Features
Compliant to the IEEE 802.3ba(40GBASE-SR4)
Support interoperability with IEEE 802.3ae 10GBASE-SR modules of various form factors such as SFP+, XFP, X2
Compliant to the QSFP+ MSA SFF-8436 Specification
Up to 100m on OM3 and 150m on OM4 MMF
VCSEL array transmitter and PIN array receiver
Single 3.3V Power Supply and Power dissipation < 1.5W
Operates at 10.3125Gbps per channel
Operating case temperature: 0°C to +70°C
I2C interface with integrated Digital℃ Diagnostic℃ Monitoring
Utilizes a standard 12/8 lane optical fiber with MPO connector
Applications
40GBE and 10GBE interconnects
Datacom/Telecom switch & router connections
Data aggregation and backplane applications
Proprietary protocol and density application
-
Module Block Diagram
Absolute Maximum Ratings
Parameter
Symbol
Min.
Typical
Max.
Unit
Power Supply Voltage
VCC
0
3.6
V
Storage Temperature
Ts
-40
+85
°C
Relative Humidity
RH
0
85
%
RX Input Average Power per Lane
Pmax
-
5.5
dBm
Recommended Operating Environment
Parameter
Symbol
Min.
Typical
Max.
Unit
Power Supply Voltage
VCC
3.13
3.3
3.46
V
Power Supply Current
ICC
1000
mA
Power Dissipation
PD
3.5
W
Operating Case Temperature
TC
0
+70
°C
Aggregate Data Rate
-
103.125
Gbps
Bit Rate per Lane
BR
25.78125
Gbps
Electrical CharacteristicsParameter
Symbol
Min.
Typical
Max.
Unit
Note
Transmitter Section
Input Differential Impedance
Rin
90
100
110
Ω
Differential Data Input Swing
Vin PP
180
1000
mV
1
Receiver Section
Differential Data Output Swing
Vout PP
300
850
mV
Notes:
- Connected directly to TX data input pins. AC coupling from pins into laser driver IC.
- Transceiver temperature
- Transceiver temperature
Optical Parameters
Parameter
Symbol
Min.
Typical
Max.
Unit
Note
Transmitter Section
Lane Centre Wavelength (range)
λ0
1294.53
1296.59
nm
λ1
1299.02
1301.09
nm
λ2
1303.54
1305.63
nm
λ3
1308.09
1310.19
nm
Spectral Width (-20dB)
Δλ
1
nm
Side Mode Suppression Ratio
SMSR
30
dB
Average Optical Power per Lane
Pout
-4.3
+4.5
dBm
1
OMA Power per Lane
OMA
-1.3
4.5
dBm
1
Laser Off Power per Lane
Poff
-
-
-30
dBm
Extinction Ratio
ER
4
-
-
dB
2
Relative Intensity Noise
RIN
-
-
-128
dB/Hz
Optical Return Loss Tolerance
-
-
20
dB
Transmitter eye mask definition
{X1, X2, X3, Y1, Y2, Y3}
Compliant with IEEE802.3bm
{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}
2
Receiver Section
Lane Center Wavelength (range)
λ0
1294.53
1296.59
nm
λ1
1299.02
1301.09
nm
λ2
1303.54
1305.63
nm
λ3
1308.09
1310.19
nm
Average Receiver Power per Lane
RXPX
-10.6
4.5
dBm
3
OMA Sensitivity per Lane
RXsens
-8.6
dBm
3
Los Assert
LOSA
-24
-
-
dBm
Los Dessert
LOSD
-
-
-11.6
dBm
Los Hysteresis
LOSH
0.5
-
5
dB
Overload per Lane
Pin-max
-
-
4.5
dBm
3
Receiver Reflectance
-
-
-12
dB
Damage Threshold per Lane
-
-
5.5
dBm
Notes:
1. The optical power is launched into 9/125µm SMF.
2. Measured with a PRBS 231-1 test pattern @25.78Gbps.
3. Measured with a PRBS 231-1 test pattern @25.78Gbps, ER=4dB, BER <10-12.
Pin Descriptions
Pin
Symbol
Description
Plug Seq.
Notes
1
Ground
Ground
1
1
2
Tx2n
Transmitter Inverted Data Input
3
3
Tx2p
Transmitter Non-Inverted Data Input
3
4
Ground
Ground
1
1
5
Tx4n
Transmitter Inverted Data Input
3
6
Tx4p
Transmitter Non-Inverted Data Input
3
7
Ground
Ground
1
1
8
ModSelL
Module Select
3
9
ResetL
Module Reset
3
10
VccRx
+3.3 V Power supply receiver
2
2
11
SCL
2-wire serial interface clock
3
12
SDA
2-wire serial interface data
3
13
Ground
Ground
1
1
14
Rx3p
Transmitter Non-Inverted Data Input
3
15
Rx3n
Transmitter Inverted Data Input
3
16
Ground
Ground
1
1
17
Rx1p
Transmitter Non-Inverted Data Input
3
18
Rx1n
Transmitter Inverted Data Input
3
19
Ground
Ground
1
1
20
Ground
Ground
1
1
21
Rx2n
Transmitter Inverted Data Input
3
22
Rx2p
Transmitter Non-Inverted Data Input
3
23
Ground
Ground
1
1
24
Rx4n
Transmitter Inverted Data Input
3
25
Rx4p
Transmitter Non-Inverted Data Input
3
26
Ground
Ground
1
1
27
ModPrsL
Module Present
3
28
IntL
Interrupt
3
29
VccTx
+3.3 V Power supply transmitter
2
2
30
Vcc1
+3.3 V Power Supply
2
2
31
LPMode
Low Power Mode
3
32
Ground
Ground
1
1
33
Tx3p
Transmitter Non-Inverted Data Input
3
34
Tx3n
Transmitter Inverted Data Input
3
35
Ground
Ground
1
1
36
Tx1p
Transmitter Non-Inverted Data Input
3
37
Tx1n
Transmitter Inverted Data Input
3
38
Ground
Ground
1
1
Notes:
Plug Seq.: Pin engagement sequence during hot plugging.
1. Module ground pins GND are isolated from the module case.
2. VccRx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently.
Recommended Power Interface Circuit
Recommended Interface Circuit
Digital Diagnostic FunctionsThe QSFP28 transceivers support the 2-wire serial communication protocol as defined in the QSFP28 MSA, which allows real-time access to the following operating parameters:
- Laser bias current
- Transmitted optical power
- Received optical power
- Transceiver supply voltage
It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 QSFP28 Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0 and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP28 MSA Specification.
- Connected directly to TX data input pins. AC coupling from pins into laser driver IC.
-
Mechanical Dimensions
-
Part Number
Product Description
GY21H-3110
100Gbps QSFP28 LR4, 10km on SMF, 0ºC ~ +70ºC, With DDM.
Key words:
GYLQ-161L-10-L，100Gbps 10km LR4 Duplex LC QSFP28
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